This invention is especially useful in digital integrated circuits with high speed CMOS buffer circuits capable of driving large capacitive loads, restoring slow transitioning digital signals, or driving highly resistive RC interconnects lines.

CMOS technology is conventionally used to implement digital integrated circuits. Often CMOS circuits drive large capacitive loads. Such capacitive loads may occur due to on-chip interconnections, output pads, or off chip-loads. The CMOS circuit commonly used for driving large capacitive loads is the tapered buffer. This invention provides a buffer circuit for transmitting digital data signals from an input to output of the buffer for any frequency of input data signals with higher speed and less dissipated power than prior buffer circuit designs. It uses a buffer circuit with one or more nulling transistors coupled with driving transistors which eliminate the parasitic capacitance of the buffer circuit. The circuit further restores slow transitioning signals with minimal delay and power dissipation and is capable of driving a highly resistive interconnect data line, having capacitance which can be inserted at multiple locations along the line.

Digital Buffer Circuits

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